The wider the trace, the less impedance presented to the circuit.

Do not locate clock signals near I/O areas. For traces within two inches of I/O, use the lowest-speed logic device possible. For traces within 3 inches of I/O circuits use minimum-speed logic. This is not a requirement when functional partitioning is implemented.

Keep impedance of traces balanced and short to minimize reflections and functionality degradation.

Design clock traces as transmission lines to minimize or prevent reflections, ringing and creations of RF common-mode currents.

If traces must be electrically long, route the trace using transmission line theory.

Terminate all clock traces in their characteristics impedance.

Route clock traces on one routing plane only. This layer must be adjacent to a solid reference (image) plane at all times. If possible, route all clock traces stripline. Traces on the bottom of the board are still microstrip.

Do not layer jump clock or high-threat traces between different layers. Doing so disrupts RF coupling between the trace and an image plane. Disruption prevents RF return current from completing its route uninterrupted from source to load in a continuous manner. If traces must jump between planes, use ground vias at each and every layer jump to maintain image plane continuity.

Microstrip allows for fastest transition of signal edges while permitting greater amount of RF currents to be radiated from the trace.Stripline allows for optimal suppression of RF currents, but at the expense of slowing down signal edges (in the picosecond range) due to capacitive loading between the trace and surrounding reference planes.