About Excellon (Drill) files and tool (bit) lists 
Excellon drill files are used to determine what size holes to drill and where. Plated and non-plated holes need to be included in one drill file, with plated and non-plated holes having different tool numbers.

A tool list is used in combination with The Excellon drill file to create the drill map. The drill file specifies where to place the holes. The tool list specifies what tool to use. A tool list should be embedded in the Excellon file or sent as a separate text file. Using a tool list provided on a fabrication drawing is not preferable, as it eliminates many of the automatic verifications and makes data entry errors far more likely.

Recommendation: A standard format for example is Excellon format, ASCII Odd/ None, 2.4 Trailing Zero Suppression, English Units, No Step and Repeats. Nearly all layout packages will output an excellon drill file. If there are problems to generate one, the designer has to study the manuals, ask the company which developed the PCBsoftware, or in some cases ask the manufacturer to create one from the fabrication drawing. Tool list have to be embedded in Excellon drill file or sent as a separate text file. If the PCB layout software will output an Excellon drill file, it will also output a tool list. Common extensions include .tol and .rep. 

Insufficient Annular Ring
An annular ring is the donut (“annulus”) created when the drill bit pierces a copper layer. It is defined as "the radius" of this donut, in fact (Dpad - Dhole)/2. For example, a .030” (30 mil) pad with a .020” (20 mil) hole would have a .005” (5 mil) annular ring. This is required to allow for complete plating on vias, as well as solderability on component holes. Many times people do not allow for the proper annular ring requirements.

Recommendation:  A minimum of .005” (5 mil) annular ring for vias or a minimum of .007”  (7 mil) for component holes is required for manufacturing. In practice, the designer is adviced to increase these values to not be at the edge of the PCB manufacturing process. For instance, a via having a .040” (40 mil) pad, a .020” (20 mil) hole, and a .010” (10 mil) annular ring is a very good design solution. Almost all PCB layout packages provide this verification as a DFM check. Setting sufficient annular ring in the layout is the preferred method in order to maintain proper copper spacing.