• Enhancement-load NMOS gain stage

 

 

Resistor R_L used in the simple gain stage is undesirable in IC realisation

Usually replaced by a second MOSFET

NMOS enhancement-mode device used in the Figure as Q₂

Q₂ is in the saturation - ensured by the short connection between drain and gate
                                                                                              (v_ds > v_gs - V_T)

Q₂ behaves like a resistor of value:

 

Voltage gain:

 

 

If the body effect is small (  ):

 

Disadvantages:

Large gain can only be obtained if the "aspect ratio" of Q₁ is much larger than that of Q₂

This requires large silicon area

Reduced dynamic range (v_out < V_DD - V_T must be satisfied in order to keep the load device conducting)