Consider a differential-input, single-ended-output MOS gain stage shown in the following figure:

 

Suppose the following dimensions and parameters of the MOS structure:

      All transistors have the same gate width to length ratio W/L = (100 μm) / (1.6 μm),

      Mobility of electrons near the silicon surface μ_n = 0.05 m2V-1s-1,

      Gate capacitance per unit area C_ox = 1.9 10-3 pF μm-2,

      Transistor threshold voltage V_tn = 0.8 V,

      Small-signal drain-source resistance r_DS = 8 106 L / I_D,

      Bias current I_bias = 200 μA.

 

1. Find the output impedance r_out.
2. Find the gain from the differential input V_in to the output V_out.