CMOS Technology Nodes

 

            Defined by the channel effective length L

 

 

CMOS Technology Scaling

 

Example:

1.5 μm   1 μm   0.8 μm   0.6 μm   0.35 μm   0.25 μm   0.18 μm   0.12 μm   0.1 μm   ...

 

Technology-node cycle

                        Period of time in which a new technology node is reached

 

                        Achievement of an approximate      0.7x reduction per node

                                                                              (0.5x per two nodes)                  

 

 

            Motivations

                        Better performance

                        Less power consumption

                        Smaller Silicon area

                        Lower cost

 

Related Reading

Gregorian, R., Temes G. C., Analog MOS integrated circuits for signal processing, Wiley, 1986.

Johns, D. A., Martin, K., Analog integrated circuit design, Wiley, 1997.

Razavi, B., RF Microelectronics, Prentice Hall, 1998.